In designing an integrated circuit (IC), engineers typically rely upon computer simulation tools to help create a schematic circuit design consisting of individual circuit elements electrically coupled together in order to perform certain functions. To actually fabricate this integrated circuit in a semiconductor substrate, the circuit design must be translated into a physical representation, or layout, which itself can then be transferred onto a series of templates (e.g. masks) used to sequentially pattern layers in or on the semiconductor substrate surface. Electronic Design Automation (EDA) tools assist layout designers in the task of translating the circuit design into a series of two-dimensional patterns that will define the component layers of the IC, such as the active device regions, gate electrodes, contact holes, metal interconnections, and so on.
A method of transferring a layout pattern to the semiconductor substrate surface is to use the process of optical lithography (photolithography) in which the layout pattern is first transferred onto a physical template that in turn is used to optically project the layout pattern onto the surface of the semiconductor substrate (wafer).
In transferring the IC layout to physical templates, a mask is generally created for each layer of the IC. For example, the data representing the layout pattern for a specific layer (e.g. the gate electrode layer) can be input into an electron beam machine that writes the layout pattern onto a blank mask. After the mask is made, it is used to optically project the layout pattern onto many wafers, one at a time. This optical projection is done by shining light through the mask onto the wafer. Optical lenses and/or mirrors may be used to direct, demagnify, and/or focus the mask image onto the wafer surface. Prior to exposure, the wafer is first coated with a masking layer of photosensitive material that is resistant to being etched and is hence referred to as photoresist.
For a binary mask, light passes through the clear regions of the mask, thereby exposing the photoresist coating in these regions. In contrast, light is blocked by the opaque regions of the binary mask, thereby leaving the photoresist coating unexposed in these regions. When the photoresist coating is then developed in a chemical solution, either the exposed regions (for a positive photoresist) or unexposed regions (for a negative photoresist) are selectively removed. The end result is a wafer coated with a layer of photoresist exhibiting a desired pattern to define the geometries, features, lines, and shapes of an underlying layer or an overlying layer. The photoresist layer is then removed after the underlying layer is processed (e.g. etched) or after the overlying layer is deposited, respectively. This photolithography process is used to define each layer of the IC, generally using a separate mask for each layer.
With the increased density of semiconductor devices, the sheet resistivity of the electrically-conducting structures of these devices, such as the gate, drain and source regions of metal oxide semiconductor (MOS) transistors, the emitters of bipolar transistors, the local interconnect regions of MOS and bipolar transistors, and the interconnect lines connecting these devices together, is beginning to limit the speed at which semiconductor devices can operate.
One well-known technique for reducing the sheet resistivity of silicon structures is to form a layer of metal silicide over the silicon structure. The resulting silicided structures provide the lower resistivity of a metal silicide along with the well-known attributes of silicon. The silicide regions may be formed using a combination of masks as described above. The silicide regions play an important role in modern semiconductor devices. It is therefore desirable to have improved methods of silicide formation.